1// Copyright 2016 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5// GOPPC64 values indicate power8, power9, etc.
6// That means the code is compiled for that target,
7// and will not run on earlier targets.
8//
9(Add(Ptr|64|32|16|8) ...) => (ADD ...)
10(Add64F ...) => (FADD ...)
11(Add32F ...) => (FADDS ...)
12
13(Sub(Ptr|64|32|16|8) ...) => (SUB ...)
14(Sub32F ...) => (FSUBS ...)
15(Sub64F ...) => (FSUB ...)
16
17// Combine 64 bit integer multiply and adds
18(ADD l:(MULLD x y) z) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD x y z)
19
20(Mod16 x y) => (Mod32 (SignExt16to32 x) (SignExt16to32 y))
21(Mod16u x y) => (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y))
22(Mod8 x y) => (Mod32 (SignExt8to32 x) (SignExt8to32 y))
23(Mod8u x y) => (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y))
24(Mod64 x y) && buildcfg.GOPPC64 >=9 => (MODSD x y)
25(Mod64 x y) && buildcfg.GOPPC64 <=8 => (SUB x (MULLD y (DIVD x y)))
26(Mod64u x y) && buildcfg.GOPPC64 >= 9 => (MODUD x y)
27(Mod64u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLD y (DIVDU x y)))
28(Mod32 x y) && buildcfg.GOPPC64 >= 9 => (MODSW x y)
29(Mod32 x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVW x y)))
30(Mod32u x y) && buildcfg.GOPPC64 >= 9 => (MODUW x y)
31(Mod32u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVWU x y)))
32
33// (x + y) / 2 with x>=y => (x - y) / 2 + y
34(Avg64u <t> x y) => (ADD (SRDconst <t> (SUB <t> x y) [1]) y)
35
36(Mul64 ...) => (MULLD ...)
37(Mul(32|16|8) ...) => (MULLW ...)
38(Select0 (Mul64uhilo x y)) => (MULHDU x y)
39(Select1 (Mul64uhilo x y)) => (MULLD x y)
40
41(Div64 [false] x y) => (DIVD x y)
42(Div64u ...) => (DIVDU ...)
43(Div32 [false] x y) => (DIVW x y)
44(Div32u ...) => (DIVWU ...)
45(Div16 [false] x y) => (DIVW (SignExt16to32 x) (SignExt16to32 y))
46(Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
47(Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y))
48(Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))
49
50(Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...)
51
52(Mul(32|64)F ...) => ((FMULS|FMUL) ...)
53
54(Div(32|64)F ...) => ((FDIVS|FDIV) ...)
55
56// Lowering float <=> int
57(Cvt32to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD (SignExt32to64 x)))
58(Cvt64to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD x))
59
60(Cvt32Fto(32|64) x) => (MFVSRD (FCTI(W|D)Z x))
61(Cvt64Fto(32|64) x) => (MFVSRD (FCTI(W|D)Z x))
62
63(Cvt32Fto64F ...) => (Copy ...) // Note v will have the wrong type for patterns dependent on Float32/Float64
64(Cvt64Fto32F ...) => (FRSP ...)
65
66(CvtBoolToUint8 ...) => (Copy ...)
67
68(Round(32|64)F ...) => (LoweredRound(32|64)F ...)
69
70(Sqrt ...) => (FSQRT ...)
71(Sqrt32 ...) => (FSQRTS ...)
72(Floor ...) => (FFLOOR ...)
73(Ceil ...) => (FCEIL ...)
74(Trunc ...) => (FTRUNC ...)
75(Round ...) => (FROUND ...)
76(Copysign x y) => (FCPSGN y x)
77(Abs ...) => (FABS ...)
78(FMA ...) => (FMADD ...)
79
80// Lowering extension
81// Note: we always extend to 64 bits even though some ops don't need that many result bits.
82(SignExt8to(16|32|64) ...) => (MOVBreg ...)
83(SignExt16to(32|64) ...) => (MOVHreg ...)
84(SignExt32to64 ...) => (MOVWreg ...)
85
86(ZeroExt8to(16|32|64) ...) => (MOVBZreg ...)
87(ZeroExt16to(32|64) ...) => (MOVHZreg ...)
88(ZeroExt32to64 ...) => (MOVWZreg ...)
89
90(Trunc(16|32|64)to8 <t> x) && t.IsSigned() => (MOVBreg x)
91(Trunc(16|32|64)to8 x) => (MOVBZreg x)
92(Trunc(32|64)to16 <t> x) && t.IsSigned() => (MOVHreg x)
93(Trunc(32|64)to16 x) => (MOVHZreg x)
94(Trunc64to32 <t> x) && t.IsSigned() => (MOVWreg x)
95(Trunc64to32 x) => (MOVWZreg x)
96
97// Lowering constants
98(Const(64|32|16|8) [val]) => (MOVDconst [int64(val)])
99(Const(32|64)F ...) => (FMOV(S|D)const ...)
100(ConstNil) => (MOVDconst [0])
101(ConstBool [t]) => (MOVDconst [b2i(t)])
102
103// Carrying addition.
104(Select0 (Add64carry x y c)) => (Select0 <typ.UInt64> (ADDE x y (Select1 <typ.UInt64> (ADDCconst c [-1]))))
105(Select1 (Add64carry x y c)) => (ADDZEzero (Select1 <typ.UInt64> (ADDE x y (Select1 <typ.UInt64> (ADDCconst c [-1])))))
106// Fold initial carry bit if 0.
107(ADDE x y (Select1 <typ.UInt64> (ADDCconst (MOVDconst [0]) [-1]))) => (ADDC x y)
108// Fold transfer of CA -> GPR -> CA. Note 2 uses when feeding into a chained Add64carry.
109(Select1 (ADDCconst n:(ADDZEzero x) [-1])) && n.Uses <= 2 => x
110
111// Borrowing subtraction.
112(Select0 (Sub64borrow x y c)) => (Select0 <typ.UInt64> (SUBE x y (Select1 <typ.UInt64> (SUBCconst c [0]))))
113(Select1 (Sub64borrow x y c)) => (NEG (SUBZEzero (Select1 <typ.UInt64> (SUBE x y (Select1 <typ.UInt64> (SUBCconst c [0]))))))
114// Fold initial borrow bit if 0.
115(SUBE x y (Select1 <typ.UInt64> (SUBCconst (MOVDconst [0]) [0]))) => (SUBC x y)
116// Fold transfer of CA -> GPR -> CA. Note 2 uses when feeding into a chained Sub64borrow.
117(Select1 (SUBCconst n:(NEG (SUBZEzero x)) [0])) && n.Uses <= 2 => x
118
119// Constant folding
120(FABS (FMOVDconst [x])) => (FMOVDconst [math.Abs(x)])
121(FSQRT (FMOVDconst [x])) && x >= 0 => (FMOVDconst [math.Sqrt(x)])
122(FFLOOR (FMOVDconst [x])) => (FMOVDconst [math.Floor(x)])
123(FCEIL (FMOVDconst [x])) => (FMOVDconst [math.Ceil(x)])
124(FTRUNC (FMOVDconst [x])) => (FMOVDconst [math.Trunc(x)])
125
126// Rotates
127(RotateLeft8 <t> x (MOVDconst [c])) => (Or8 (Lsh8x64 <t> x (MOVDconst [c&7])) (Rsh8Ux64 <t> x (MOVDconst [-c&7])))
128(RotateLeft16 <t> x (MOVDconst [c])) => (Or16 (Lsh16x64 <t> x (MOVDconst [c&15])) (Rsh16Ux64 <t> x (MOVDconst [-c&15])))
129(RotateLeft(32|64) ...) => ((ROTLW|ROTL) ...)
130
131// Constant rotate generation
132(ROTLW x (MOVDconst [c])) => (ROTLWconst x [c&31])
133(ROTL x (MOVDconst [c])) => (ROTLconst x [c&63])
134
135// Combine rotate and mask operations
136(Select0 (ANDCCconst [m] (ROTLWconst [r] x))) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,m,32)] x)
137(AND (MOVDconst [m]) (ROTLWconst [r] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,m,32)] x)
138(Select0 (ANDCCconst [m] (ROTLW x r))) && isPPC64WordRotateMask(m) => (RLWNM [encodePPC64RotateMask(0,m,32)] x r)
139(AND (MOVDconst [m]) (ROTLW x r)) && isPPC64WordRotateMask(m) => (RLWNM [encodePPC64RotateMask(0,m,32)] x r)
140
141// Note, any rotated word bitmask is still a valid word bitmask.
142(ROTLWconst [r] (AND (MOVDconst [m]) x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,rotateLeft32(m,r),32)] x)
143(ROTLWconst [r] (Select0 (ANDCCconst [m] x))) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,rotateLeft32(m,r),32)] x)
144
145(Select0 (ANDCCconst [m] (SRWconst x [s]))) && mergePPC64RShiftMask(m,s,32) == 0 => (MOVDconst [0])
146(Select0 (ANDCCconst [m] (SRWconst x [s]))) && mergePPC64AndSrwi(m,s) != 0 => (RLWINM [mergePPC64AndSrwi(m,s)] x)
147(AND (MOVDconst [m]) (SRWconst x [s])) && mergePPC64RShiftMask(m,s,32) == 0 => (MOVDconst [0])
148(AND (MOVDconst [m]) (SRWconst x [s])) && mergePPC64AndSrwi(m,s) != 0 => (RLWINM [mergePPC64AndSrwi(m,s)] x)
149
150(SRWconst (Select0 (ANDCCconst [m] x)) [s]) && mergePPC64RShiftMask(m>>uint(s),s,32) == 0 => (MOVDconst [0])
151(SRWconst (Select0 (ANDCCconst [m] x)) [s]) && mergePPC64AndSrwi(m>>uint(s),s) != 0 => (RLWINM [mergePPC64AndSrwi(m>>uint(s),s)] x)
152(SRWconst (AND (MOVDconst [m]) x) [s]) && mergePPC64RShiftMask(m>>uint(s),s,32) == 0 => (MOVDconst [0])
153(SRWconst (AND (MOVDconst [m]) x) [s]) && mergePPC64AndSrwi(m>>uint(s),s) != 0 => (RLWINM [mergePPC64AndSrwi(m>>uint(s),s)] x)
154
155// Merge shift right + shift left and clear left (e.g for a table lookup)
156(CLRLSLDI [c] (SRWconst [s] x)) && mergePPC64ClrlsldiSrw(int64(c),s) != 0 => (RLWINM [mergePPC64ClrlsldiSrw(int64(c),s)] x)
157(SLDconst [l] (SRWconst [r] x)) && mergePPC64SldiSrw(l,r) != 0 => (RLWINM [mergePPC64SldiSrw(l,r)] x)
158// The following reduction shows up frequently too. e.g b[(x>>14)&0xFF]
159(CLRLSLDI [c] i:(RLWINM [s] x)) && mergePPC64ClrlsldiRlwinm(c,s) != 0 => (RLWINM [mergePPC64ClrlsldiRlwinm(c,s)] x)
160
161// large constant signed right shift, we leave the sign bit
162(Rsh64x64 x (MOVDconst [c])) && uint64(c) >= 64 => (SRADconst x [63])
163(Rsh32x64 x (MOVDconst [c])) && uint64(c) >= 32 => (SRAWconst x [63])
164(Rsh16x64 x (MOVDconst [c])) && uint64(c) >= 16 => (SRAWconst (SignExt16to32 x) [63])
165(Rsh8x64 x (MOVDconst [c])) && uint64(c) >= 8 => (SRAWconst (SignExt8to32 x) [63])
166
167// constant shifts
168((Lsh64|Rsh64|Rsh64U)x64 x (MOVDconst [c])) && uint64(c) < 64 => (S(L|RA|R)Dconst x [c])
169((Lsh32|Rsh32|Rsh32U)x64 x (MOVDconst [c])) && uint64(c) < 32 => (S(L|RA|R)Wconst x [c])
170((Rsh16|Rsh16U)x64 x (MOVDconst [c])) && uint64(c) < 16 => (SR(AW|W)const ((Sign|Zero)Ext16to32 x) [c])
171(Lsh16x64 x (MOVDconst [c])) && uint64(c) < 16 => (SLWconst x [c])
172((Rsh8|Rsh8U)x64 x (MOVDconst [c])) && uint64(c) < 8 => (SR(AW|W)const ((Sign|Zero)Ext8to32 x) [c])
173(Lsh8x64 x (MOVDconst [c])) && uint64(c) < 8 => (SLWconst x [c])
174
175// Lower bounded shifts first. No need to check shift value.
176(Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y)
177(Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y)
178(Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y)
179(Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y)
180(Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y)
181(Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW x y)
182(Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD (MOVHZreg x) y)
183(Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD (MOVBZreg x) y)
184(Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD x y)
185(Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW x y)
186(Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD (MOVHreg x) y)
187(Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD (MOVBreg x) y)
188
189// Unbounded shifts. Go shifts saturate to 0 or -1 when shifting beyond the number of
190// bits in a type, PPC64 shifts do not (see the ISA for details).
191//
192// Note, y is always non-negative.
193//
194// Note, ISELZ is intentionally not used in lower. Where possible, ISEL is converted to ISELZ in late lower
195// after all the ISEL folding rules have been exercised.
196
197((Rsh64U|Lsh64)x64 <t> x y) => (ISEL [0] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPUconst y [64]))
198((Rsh64U|Lsh64)x32 <t> x y) => (ISEL [0] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPWUconst y [64]))
199((Rsh64U|Lsh64)x16 <t> x y) => (ISEL [2] (S(R|L)D <t> x y) (MOVDconst [0]) (Select1 <types.TypeFlags> (ANDCCconst [0xFFC0] y)))
200((Rsh64U|Lsh64)x8 <t> x y) => (ISEL [2] (S(R|L)D <t> x y) (MOVDconst [0]) (Select1 <types.TypeFlags> (ANDCCconst [0x00C0] y)))
201(Rsh64x(64|32) <t> x y) => (ISEL [0] (SRAD <t> x y) (SRADconst <t> x [63]) (CMP(U|WU)const y [64]))
202(Rsh64x16 <t> x y) => (ISEL [2] (SRAD <t> x y) (SRADconst <t> x [63]) (Select1 <types.TypeFlags> (ANDCCconst [0xFFC0] y)))
203(Rsh64x8 <t> x y) => (ISEL [2] (SRAD <t> x y) (SRADconst <t> x [63]) (Select1 <types.TypeFlags> (ANDCCconst [0x00C0] y)))
204
205((Rsh32U|Lsh32)x64 <t> x y) => (ISEL [0] (S(R|L)W <t> x y) (MOVDconst [0]) (CMPUconst y [32]))
206((Rsh32U|Lsh32)x32 <t> x y) => (ISEL [0] (S(R|L)W <t> x y) (MOVDconst [0]) (CMPWUconst y [32]))
207((Rsh32U|Lsh32)x16 <t> x y) => (ISEL [2] (S(R|L)W <t> x y) (MOVDconst [0]) (Select1 <types.TypeFlags> (ANDCCconst [0xFFE0] y)))
208((Rsh32U|Lsh32)x8 <t> x y) => (ISEL [2] (S(R|L)W <t> x y) (MOVDconst [0]) (Select1 <types.TypeFlags> (ANDCCconst [0x00E0] y)))
209(Rsh32x(64|32) <t> x y) => (ISEL [0] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMP(U|WU)const y [32]))
210(Rsh32x16 <t> x y) => (ISEL [2] (SRAW <t> x y) (SRAWconst <t> x [31]) (Select1 <types.TypeFlags> (ANDCCconst [0xFFE0] y)))
211(Rsh32x8 <t> x y) => (ISEL [2] (SRAW <t> x y) (SRAWconst <t> x [31]) (Select1 <types.TypeFlags> (ANDCCconst [0x00E0] y)))
212
213((Rsh16U|Lsh16)x64 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (CMPUconst y [16]))
214((Rsh16U|Lsh16)x32 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (CMPWUconst y [16]))
215((Rsh16U|Lsh16)x16 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (Select1 <types.TypeFlags> (ANDCCconst [0xFFF0] y)))
216((Rsh16U|Lsh16)x8 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (Select1 <types.TypeFlags> (ANDCCconst [0x00F0] y)))
217(Rsh16x(64|32) <t> x y) => (ISEL [0] (SRAD <t> (MOVHreg x) y) (SRADconst <t> (MOVHreg x) [15]) (CMP(U|WU)const y [16]))
218(Rsh16x16 <t> x y) => (ISEL [2] (SRAD <t> (MOVHreg x) y) (SRADconst <t> (MOVHreg x) [15]) (Select1 <types.TypeFlags> (ANDCCconst [0xFFF0] y)))
219(Rsh16x8 <t> x y) => (ISEL [2] (SRAD <t> (MOVHreg x) y) (SRADconst <t> (MOVHreg x) [15]) (Select1 <types.TypeFlags> (ANDCCconst [0x00F0] y)))
220
221((Rsh8U|Lsh8)x64 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (CMPUconst y [8]))
222((Rsh8U|Lsh8)x32 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (CMPWUconst y [8]))
223((Rsh8U|Lsh8)x16 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (Select1 <types.TypeFlags> (ANDCCconst [0xFFF8] y)))
224((Rsh8U|Lsh8)x8 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (Select1 <types.TypeFlags> (ANDCCconst [0x00F8] y)))
225(Rsh8x(64|32) <t> x y) => (ISEL [0] (SRAD <t> (MOVBreg x) y) (SRADconst <t> (MOVBreg x) [7]) (CMP(U|WU)const y [8]))
226(Rsh8x16 <t> x y) => (ISEL [2] (SRAD <t> (MOVBreg x) y) (SRADconst <t> (MOVBreg x) [7]) (Select1 <types.TypeFlags> (ANDCCconst [0xFFF8] y)))
227(Rsh8x8 <t> x y) => (ISEL [2] (SRAD <t> (MOVBreg x) y) (SRADconst <t> (MOVBreg x) [7]) (Select1 <types.TypeFlags> (ANDCCconst [0x00F8] y)))
228
229// Catch bounded shifts in situations like foo<<uint(shift&63) which might not be caught by the prove pass.
230(CMP(U|WU)const [d] (Select0 (ANDCCconst z [c]))) && uint64(d) > uint64(c) => (FlagLT)
231
232(ORN x (MOVDconst [-1])) => x
233
234(S(RAD|RD|LD) x (MOVDconst [c])) => (S(RAD|RD|LD)const [c&63 | (c>>6&1*63)] x)
235(S(RAW|RW|LW) x (MOVDconst [c])) => (S(RAW|RW|LW)const [c&31 | (c>>5&1*31)] x)
236
237(Addr {sym} base) => (MOVDaddr {sym} [0] base)
238(LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVDaddr {sym} (SPanchored base mem))
239(LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVDaddr {sym} base)
240(OffPtr [off] ptr) => (ADD (MOVDconst <typ.Int64> [off]) ptr)
241(MOVDaddr {sym} [n] p:(ADD x y)) && sym == nil && n == 0 => p
242(MOVDaddr {sym} [n] ptr) && sym == nil && n == 0 && (ptr.Op == OpArgIntReg || ptr.Op == OpPhi) => ptr
243
244// TODO: optimize these cases?
245(Ctz32NonZero ...) => (Ctz32 ...)
246(Ctz64NonZero ...) => (Ctz64 ...)
247
248(Ctz64 x) && buildcfg.GOPPC64<=8 => (POPCNTD (ANDN <typ.Int64> (ADDconst <typ.Int64> [-1] x) x))
249(Ctz64 x) => (CNTTZD x)
250(Ctz32 x) && buildcfg.GOPPC64<=8 => (POPCNTW (MOVWZreg (ANDN <typ.Int> (ADDconst <typ.Int> [-1] x) x)))
251(Ctz32 x) => (CNTTZW (MOVWZreg x))
252(Ctz16 x) => (POPCNTW (MOVHZreg (ANDN <typ.Int16> (ADDconst <typ.Int16> [-1] x) x)))
253(Ctz8 x) => (POPCNTB (MOVBZreg (ANDN <typ.UInt8> (ADDconst <typ.UInt8> [-1] x) x)))
254
255(BitLen64 x) => (SUBFCconst [64] (CNTLZD <typ.Int> x))
256(BitLen32 x) => (SUBFCconst [32] (CNTLZW <typ.Int> x))
257
258(PopCount64 ...) => (POPCNTD ...)
259(PopCount(32|16|8) x) => (POPCNT(W|W|B) (MOV(W|H|B)Zreg x))
260
261(And(64|32|16|8) ...) => (AND ...)
262(Or(64|32|16|8) ...) => (OR ...)
263(Xor(64|32|16|8) ...) => (XOR ...)
264
265(Neg(64|32|16|8) ...) => (NEG ...)
266(Neg(64|32)F ...) => (FNEG ...)
267
268(Com(64|32|16|8) x) => (NOR x x)
269
270// Lowering boolean ops
271(AndB ...) => (AND ...)
272(OrB ...) => (OR ...)
273(Not x) => (XORconst [1] x)
274
275// Merge logical operations
276(AND x (NOR y y)) => (ANDN x y)
277(OR x (NOR y y)) => (ORN x y)
278
279// Lowering comparisons
280(EqB x y) => (Select0 <typ.Int> (ANDCCconst [1] (EQV x y)))
281// Sign extension dependence on operand sign sets up for sign/zero-extension elision later
282(Eq(8|16) x y) && x.Type.IsSigned() && y.Type.IsSigned() => (Equal (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
283(Eq(8|16) x y) => (Equal (CMPW (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
284(Eq(32|64|Ptr) x y) => (Equal ((CMPW|CMP|CMP) x y))
285(Eq(32|64)F x y) => (Equal (FCMPU x y))
286
287(NeqB ...) => (XOR ...)
288// Like Eq8 and Eq16, prefer sign extension likely to enable later elision.
289(Neq(8|16) x y) && x.Type.IsSigned() && y.Type.IsSigned() => (NotEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
290(Neq(8|16) x y) => (NotEqual (CMPW (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
291(Neq(32|64|Ptr) x y) => (NotEqual ((CMPW|CMP|CMP) x y))
292(Neq(32|64)F x y) => (NotEqual (FCMPU x y))
293
294(Less(8|16) x y) => (LessThan (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
295(Less(32|64) x y) => (LessThan ((CMPW|CMP) x y))
296(Less(32|64)F x y) => (FLessThan (FCMPU x y))
297
298(Less(8|16)U x y) => (LessThan (CMPWU (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
299(Less(32|64)U x y) => (LessThan ((CMPWU|CMPU) x y))
300
301(Leq(8|16) x y) => (LessEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
302(Leq(32|64) x y) => (LessEqual ((CMPW|CMP) x y))
303(Leq(32|64)F x y) => (FLessEqual (FCMPU x y))
304
305(Leq(8|16)U x y) => (LessEqual (CMPWU (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
306(Leq(32|64)U x y) => (LessEqual (CMP(WU|U) x y))
307
308// Absorb pseudo-ops into blocks.
309(If (Equal cc) yes no) => (EQ cc yes no)
310(If (NotEqual cc) yes no) => (NE cc yes no)
311(If (LessThan cc) yes no) => (LT cc yes no)
312(If (LessEqual cc) yes no) => (LE cc yes no)
313(If (GreaterThan cc) yes no) => (GT cc yes no)
314(If (GreaterEqual cc) yes no) => (GE cc yes no)
315(If (FLessThan cc) yes no) => (FLT cc yes no)
316(If (FLessEqual cc) yes no) => (FLE cc yes no)
317(If (FGreaterThan cc) yes no) => (FGT cc yes no)
318(If (FGreaterEqual cc) yes no) => (FGE cc yes no)
319
320(If cond yes no) => (NE (CMPWconst [0] (Select0 <typ.UInt32> (ANDCCconst [1] cond))) yes no)
321
322// Absorb boolean tests into block
323(NE (CMPWconst [0] (Select0 (ANDCCconst [1] ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) cc)))) yes no) => ((EQ|NE|LT|LE|GT|GE) cc yes no)
324(NE (CMPWconst [0] (Select0 (ANDCCconst [1] ((FLessThan|FLessEqual|FGreaterThan|FGreaterEqual) cc)))) yes no) => ((FLT|FLE|FGT|FGE) cc yes no)
325
326// absorb flag constants into branches
327(EQ (FlagEQ) yes no) => (First yes no)
328(EQ (FlagLT) yes no) => (First no yes)
329(EQ (FlagGT) yes no) => (First no yes)
330
331(NE (FlagEQ) yes no) => (First no yes)
332(NE (FlagLT) yes no) => (First yes no)
333(NE (FlagGT) yes no) => (First yes no)
334
335(LT (FlagEQ) yes no) => (First no yes)
336(LT (FlagLT) yes no) => (First yes no)
337(LT (FlagGT) yes no) => (First no yes)
338
339(LE (FlagEQ) yes no) => (First yes no)
340(LE (FlagLT) yes no) => (First yes no)
341(LE (FlagGT) yes no) => (First no yes)
342
343(GT (FlagEQ) yes no) => (First no yes)
344(GT (FlagLT) yes no) => (First no yes)
345(GT (FlagGT) yes no) => (First yes no)
346
347(GE (FlagEQ) yes no) => (First yes no)
348(GE (FlagLT) yes no) => (First no yes)
349(GE (FlagGT) yes no) => (First yes no)
350
351// absorb InvertFlags into branches
352(LT (InvertFlags cmp) yes no) => (GT cmp yes no)
353(GT (InvertFlags cmp) yes no) => (LT cmp yes no)
354(LE (InvertFlags cmp) yes no) => (GE cmp yes no)
355(GE (InvertFlags cmp) yes no) => (LE cmp yes no)
356(EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
357(NE (InvertFlags cmp) yes no) => (NE cmp yes no)
358
359// constant comparisons
360(CMPWconst (MOVDconst [x]) [y]) && int32(x)==int32(y) => (FlagEQ)
361(CMPWconst (MOVDconst [x]) [y]) && int32(x)<int32(y) => (FlagLT)
362(CMPWconst (MOVDconst [x]) [y]) && int32(x)>int32(y) => (FlagGT)
363
364(CMPconst (MOVDconst [x]) [y]) && x==y => (FlagEQ)
365(CMPconst (MOVDconst [x]) [y]) && x<y => (FlagLT)
366(CMPconst (MOVDconst [x]) [y]) && x>y => (FlagGT)
367
368(CMPWUconst (MOVDconst [x]) [y]) && int32(x)==int32(y) => (FlagEQ)
369(CMPWUconst (MOVDconst [x]) [y]) && uint32(x)<uint32(y) => (FlagLT)
370(CMPWUconst (MOVDconst [x]) [y]) && uint32(x)>uint32(y) => (FlagGT)
371
372(CMPUconst (MOVDconst [x]) [y]) && x==y => (FlagEQ)
373(CMPUconst (MOVDconst [x]) [y]) && uint64(x)<uint64(y) => (FlagLT)
374(CMPUconst (MOVDconst [x]) [y]) && uint64(x)>uint64(y) => (FlagGT)
375
376// absorb flag constants into boolean values
377(Equal (FlagEQ)) => (MOVDconst [1])
378(Equal (FlagLT)) => (MOVDconst [0])
379(Equal (FlagGT)) => (MOVDconst [0])
380
381(NotEqual (FlagEQ)) => (MOVDconst [0])
382(NotEqual (FlagLT)) => (MOVDconst [1])
383(NotEqual (FlagGT)) => (MOVDconst [1])
384
385(LessThan (FlagEQ)) => (MOVDconst [0])
386(LessThan (FlagLT)) => (MOVDconst [1])
387(LessThan (FlagGT)) => (MOVDconst [0])
388
389(LessEqual (FlagEQ)) => (MOVDconst [1])
390(LessEqual (FlagLT)) => (MOVDconst [1])
391(LessEqual (FlagGT)) => (MOVDconst [0])
392
393(GreaterThan (FlagEQ)) => (MOVDconst [0])
394(GreaterThan (FlagLT)) => (MOVDconst [0])
395(GreaterThan (FlagGT)) => (MOVDconst [1])
396
397(GreaterEqual (FlagEQ)) => (MOVDconst [1])
398(GreaterEqual (FlagLT)) => (MOVDconst [0])
399(GreaterEqual (FlagGT)) => (MOVDconst [1])
400
401// absorb InvertFlags into boolean values
402((Equal|NotEqual|LessThan|GreaterThan|LessEqual|GreaterEqual) (InvertFlags x)) => ((Equal|NotEqual|GreaterThan|LessThan|GreaterEqual|LessEqual) x)
403
404
405// Elide compares of bit tests
406((EQ|NE|LT|LE|GT|GE) (CMPconst [0] (Select0 z:(ANDCCconst [c] x))) yes no) => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> z) yes no)
407((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] (Select0 z:(ANDCCconst [c] x))) yes no) => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> z) yes no)
408((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> (ANDCC x y)) yes no)
409((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(OR x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> (ORCC x y)) yes no)
410((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(XOR x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> (XORCC x y)) yes no)
411
412(CondSelect x y (SETBC [a] cmp)) => (ISEL [a] x y cmp)
413(CondSelect x y (SETBCR [a] cmp)) => (ISEL [a+4] x y cmp)
414// Only lower after bool is lowered. It should always lower. This helps ensure the folding below happens reliably.
415(CondSelect x y bool) && flagArg(bool) == nil => (ISEL [6] x y (Select1 <types.TypeFlags> (ANDCCconst [1] bool)))
416// Fold any CR -> GPR -> CR transfers when applying the above rule.
417(ISEL [6] x y (Select1 (ANDCCconst [1] (SETBC [c] cmp)))) => (ISEL [c] x y cmp)
418(ISEL [6] x y ((CMP|CMPW)const [0] (SETBC [c] cmp))) => (ISEL [c] x y cmp)
419(ISEL [6] x y ((CMP|CMPW)const [0] (SETBCR [c] cmp))) => (ISEL [c+4] x y cmp)
420
421// Lowering loads
422(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
423(Load <t> ptr mem) && is32BitInt(t) && t.IsSigned() => (MOVWload ptr mem)
424(Load <t> ptr mem) && is32BitInt(t) && !t.IsSigned() => (MOVWZload ptr mem)
425(Load <t> ptr mem) && is16BitInt(t) && t.IsSigned() => (MOVHload ptr mem)
426(Load <t> ptr mem) && is16BitInt(t) && !t.IsSigned() => (MOVHZload ptr mem)
427(Load <t> ptr mem) && t.IsBoolean() => (MOVBZload ptr mem)
428(Load <t> ptr mem) && is8BitInt(t) && t.IsSigned() => (MOVBreg (MOVBZload ptr mem)) // PPC has no signed-byte load.
429(Load <t> ptr mem) && is8BitInt(t) && !t.IsSigned() => (MOVBZload ptr mem)
430
431(Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
432(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
433
434(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
435(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
436(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
437(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
438(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
439(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
440
441// Using Zero instead of LoweredZero allows the
442// target address to be folded where possible.
443(Zero [0] _ mem) => mem
444(Zero [1] destptr mem) => (MOVBstorezero destptr mem)
445(Zero [2] destptr mem) =>
446 (MOVHstorezero destptr mem)
447(Zero [3] destptr mem) =>
448 (MOVBstorezero [2] destptr
449 (MOVHstorezero destptr mem))
450(Zero [4] destptr mem) =>
451 (MOVWstorezero destptr mem)
452(Zero [5] destptr mem) =>
453 (MOVBstorezero [4] destptr
454 (MOVWstorezero destptr mem))
455(Zero [6] destptr mem) =>
456 (MOVHstorezero [4] destptr
457 (MOVWstorezero destptr mem))
458(Zero [7] destptr mem) =>
459 (MOVBstorezero [6] destptr
460 (MOVHstorezero [4] destptr
461 (MOVWstorezero destptr mem)))
462
463(Zero [8] {t} destptr mem) => (MOVDstorezero destptr mem)
464(Zero [12] {t} destptr mem) =>
465 (MOVWstorezero [8] destptr
466 (MOVDstorezero [0] destptr mem))
467(Zero [16] {t} destptr mem) =>
468 (MOVDstorezero [8] destptr
469 (MOVDstorezero [0] destptr mem))
470(Zero [24] {t} destptr mem) =>
471 (MOVDstorezero [16] destptr
472 (MOVDstorezero [8] destptr
473 (MOVDstorezero [0] destptr mem)))
474(Zero [32] {t} destptr mem) =>
475 (MOVDstorezero [24] destptr
476 (MOVDstorezero [16] destptr
477 (MOVDstorezero [8] destptr
478 (MOVDstorezero [0] destptr mem))))
479
480// Handle cases not handled above
481// Lowered Short cases do not generate loops, and as a result don't clobber
482// the address registers or flags.
483(Zero [s] ptr mem) && buildcfg.GOPPC64 <= 8 && s < 64 => (LoweredZeroShort [s] ptr mem)
484(Zero [s] ptr mem) && buildcfg.GOPPC64 <= 8 => (LoweredZero [s] ptr mem)
485(Zero [s] ptr mem) && s < 128 && buildcfg.GOPPC64 >= 9 => (LoweredQuadZeroShort [s] ptr mem)
486(Zero [s] ptr mem) && buildcfg.GOPPC64 >= 9 => (LoweredQuadZero [s] ptr mem)
487
488// moves
489(Move [0] _ _ mem) => mem
490(Move [1] dst src mem) => (MOVBstore dst (MOVBZload src mem) mem)
491(Move [2] dst src mem) =>
492 (MOVHstore dst (MOVHZload src mem) mem)
493(Move [4] dst src mem) =>
494 (MOVWstore dst (MOVWZload src mem) mem)
495// MOVD for load and store must have offsets that are multiple of 4
496(Move [8] {t} dst src mem) =>
497 (MOVDstore dst (MOVDload src mem) mem)
498(Move [3] dst src mem) =>
499 (MOVBstore [2] dst (MOVBZload [2] src mem)
500 (MOVHstore dst (MOVHload src mem) mem))
501(Move [5] dst src mem) =>
502 (MOVBstore [4] dst (MOVBZload [4] src mem)
503 (MOVWstore dst (MOVWZload src mem) mem))
504(Move [6] dst src mem) =>
505 (MOVHstore [4] dst (MOVHZload [4] src mem)
506 (MOVWstore dst (MOVWZload src mem) mem))
507(Move [7] dst src mem) =>
508 (MOVBstore [6] dst (MOVBZload [6] src mem)
509 (MOVHstore [4] dst (MOVHZload [4] src mem)
510 (MOVWstore dst (MOVWZload src mem) mem)))
511
512// Large move uses a loop. Since the address is computed and the
513// offset is zero, any alignment can be used.
514(Move [s] dst src mem) && s > 8 && buildcfg.GOPPC64 <= 8 && logLargeCopy(v, s) =>
515 (LoweredMove [s] dst src mem)
516(Move [s] dst src mem) && s > 8 && s <= 64 && buildcfg.GOPPC64 >= 9 =>
517 (LoweredQuadMoveShort [s] dst src mem)
518(Move [s] dst src mem) && s > 8 && buildcfg.GOPPC64 >= 9 && logLargeCopy(v, s) =>
519 (LoweredQuadMove [s] dst src mem)
520
521// Calls
522// Lowering calls
523(StaticCall ...) => (CALLstatic ...)
524(ClosureCall ...) => (CALLclosure ...)
525(InterCall ...) => (CALLinter ...)
526(TailCall ...) => (CALLtail ...)
527
528// Miscellaneous
529(GetClosurePtr ...) => (LoweredGetClosurePtr ...)
530(GetCallerSP ...) => (LoweredGetCallerSP ...)
531(GetCallerPC ...) => (LoweredGetCallerPC ...)
532(IsNonNil ptr) => (NotEqual (CMPconst [0] ptr))
533(IsInBounds idx len) => (LessThan (CMPU idx len))
534(IsSliceInBounds idx len) => (LessEqual (CMPU idx len))
535(NilCheck ...) => (LoweredNilCheck ...)
536
537// Write barrier.
538(WB ...) => (LoweredWB ...)
539
540// Publication barrier as intrinsic
541(PubBarrier ...) => (LoweredPubBarrier ...)
542
543(PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem)
544(PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem)
545(PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
546
547// Optimizations
548// Note that PPC "logical" immediates come in 0:15 and 16:31 unsigned immediate forms,
549// so ORconst, XORconst easily expand into a pair.
550
551// Include very-large constants in the const-const case.
552(AND (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c&d])
553(OR (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c|d])
554(XOR (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c^d])
555(ORN (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c|^d])
556(ANDN (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c&^d])
557(NOR (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [^(c|d)])
558
559// Discover consts
560(AND x (MOVDconst [-1])) => x
561(AND x (MOVDconst [c])) && isU16Bit(c) => (Select0 (ANDCCconst [c] x))
562(XOR x (MOVDconst [c])) && isU32Bit(c) => (XORconst [c] x)
563(OR x (MOVDconst [c])) && isU32Bit(c) => (ORconst [c] x)
564
565// Simplify consts
566(ANDCCconst [c] (Select0 (ANDCCconst [d] x))) => (ANDCCconst [c&d] x)
567(ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x)
568(XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x)
569(Select0 (ANDCCconst [-1] x)) => x
570(Select0 (ANDCCconst [0] _)) => (MOVDconst [0])
571(Select1 (ANDCCconst [0] _)) => (FlagEQ)
572(XORconst [0] x) => x
573(ORconst [-1] _) => (MOVDconst [-1])
574(ORconst [0] x) => x
575
576// zero-extend of small and => small and
577(MOVBZreg y:(Select0 (ANDCCconst [c] _))) && uint64(c) <= 0xFF => y
578(MOVHZreg y:(Select0 (ANDCCconst [c] _))) && uint64(c) <= 0xFFFF => y
579(MOVWZreg y:(Select0 (ANDCCconst [c] _))) && uint64(c) <= 0xFFFFFFFF => y
580(MOVWZreg y:(AND (MOVDconst [c]) _)) && uint64(c) <= 0xFFFFFFFF => y
581
582// sign extend of small-positive and => small-positive-and
583(MOVBreg y:(Select0 (ANDCCconst [c] _))) && uint64(c) <= 0x7F => y
584(MOVHreg y:(Select0 (ANDCCconst [c] _))) && uint64(c) <= 0x7FFF => y
585(MOVWreg y:(Select0 (ANDCCconst [c] _))) && uint64(c) <= 0xFFFF => y // 0xFFFF is largest immediate constant, when regarded as 32-bit is > 0
586(MOVWreg y:(AND (MOVDconst [c]) _)) && uint64(c) <= 0x7FFFFFFF => y
587
588// small and of zero-extend => either zero-extend or small and
589(Select0 (ANDCCconst [c] y:(MOVBZreg _))) && c&0xFF == 0xFF => y
590(Select0 (ANDCCconst [0xFF] (MOVBreg x))) => (MOVBZreg x)
591(Select0 (ANDCCconst [c] y:(MOVHZreg _))) && c&0xFFFF == 0xFFFF => y
592(Select0 (ANDCCconst [0xFFFF] (MOVHreg x))) => (MOVHZreg x)
593
594(AND (MOVDconst [c]) y:(MOVWZreg _)) && c&0xFFFFFFFF == 0xFFFFFFFF => y
595(AND (MOVDconst [0xFFFFFFFF]) y:(MOVWreg x)) => (MOVWZreg x)
596// normal case
597(Select0 (ANDCCconst [c] (MOVBZreg x))) => (Select0 (ANDCCconst [c&0xFF] x))
598(Select0 (ANDCCconst [c] (MOVHZreg x))) => (Select0 (ANDCCconst [c&0xFFFF] x))
599(Select0 (ANDCCconst [c] (MOVWZreg x))) => (Select0 (ANDCCconst [c&0xFFFFFFFF] x))
600
601// Eliminate unnecessary sign/zero extend following right shift
602(MOV(B|H|W)Zreg (SRWconst [c] (MOVBZreg x))) => (SRWconst [c] (MOVBZreg x))
603(MOV(H|W)Zreg (SRWconst [c] (MOVHZreg x))) => (SRWconst [c] (MOVHZreg x))
604(MOVWZreg (SRWconst [c] (MOVWZreg x))) => (SRWconst [c] (MOVWZreg x))
605(MOV(B|H|W)reg (SRAWconst [c] (MOVBreg x))) => (SRAWconst [c] (MOVBreg x))
606(MOV(H|W)reg (SRAWconst [c] (MOVHreg x))) => (SRAWconst [c] (MOVHreg x))
607(MOVWreg (SRAWconst [c] (MOVWreg x))) => (SRAWconst [c] (MOVWreg x))
608
609(MOV(WZ|W)reg (S(R|RA)Wconst [c] x)) && sizeof(x.Type) <= 32 => (S(R|RA)Wconst [c] x)
610(MOV(HZ|H)reg (S(R|RA)Wconst [c] x)) && sizeof(x.Type) <= 16 => (S(R|RA)Wconst [c] x)
611(MOV(BZ|B)reg (S(R|RA)Wconst [c] x)) && sizeof(x.Type) == 8 => (S(R|RA)Wconst [c] x)
612
613// initial right shift will handle sign/zero extend
614(MOVBZreg (SRDconst [c] x)) && c>=56 => (SRDconst [c] x)
615(MOVBreg (SRDconst [c] x)) && c>56 => (SRDconst [c] x)
616(MOVBreg (SRDconst [c] x)) && c==56 => (SRADconst [c] x)
617(MOVBreg (SRADconst [c] x)) && c>=56 => (SRADconst [c] x)
618(MOVBZreg (SRWconst [c] x)) && c>=24 => (SRWconst [c] x)
619(MOVBreg (SRWconst [c] x)) && c>24 => (SRWconst [c] x)
620(MOVBreg (SRWconst [c] x)) && c==24 => (SRAWconst [c] x)
621(MOVBreg (SRAWconst [c] x)) && c>=24 => (SRAWconst [c] x)
622
623(MOVHZreg (SRDconst [c] x)) && c>=48 => (SRDconst [c] x)
624(MOVHreg (SRDconst [c] x)) && c>48 => (SRDconst [c] x)
625(MOVHreg (SRDconst [c] x)) && c==48 => (SRADconst [c] x)
626(MOVHreg (SRADconst [c] x)) && c>=48 => (SRADconst [c] x)
627(MOVHZreg (SRWconst [c] x)) && c>=16 => (SRWconst [c] x)
628(MOVHreg (SRWconst [c] x)) && c>16 => (SRWconst [c] x)
629(MOVHreg (SRAWconst [c] x)) && c>=16 => (SRAWconst [c] x)
630(MOVHreg (SRWconst [c] x)) && c==16 => (SRAWconst [c] x)
631
632(MOVWZreg (SRDconst [c] x)) && c>=32 => (SRDconst [c] x)
633(MOVWreg (SRDconst [c] x)) && c>32 => (SRDconst [c] x)
634(MOVWreg (SRADconst [c] x)) && c>=32 => (SRADconst [c] x)
635(MOVWreg (SRDconst [c] x)) && c==32 => (SRADconst [c] x)
636
637// Various redundant zero/sign extension combinations.
638(MOVBZreg y:(MOVBZreg _)) => y // repeat
639(MOVBreg y:(MOVBreg _)) => y // repeat
640(MOVBreg (MOVBZreg x)) => (MOVBreg x)
641(MOVBZreg (MOVBreg x)) => (MOVBZreg x)
642
643// H - there are more combinations than these
644
645(MOVHZreg y:(MOV(H|B)Zreg _)) => y // repeat
646(MOVHZreg y:(MOVHBRload _ _)) => y
647
648(MOVHreg y:(MOV(H|B)reg _)) => y // repeat
649
650(MOV(H|HZ)reg y:(MOV(HZ|H)reg x)) => (MOV(H|HZ)reg x)
651
652// W - there are more combinations than these
653
654(MOV(WZ|WZ|WZ|W|W|W)reg y:(MOV(WZ|HZ|BZ|W|H|B)reg _)) => y // repeat
655(MOVWZreg y:(MOV(H|W)BRload _ _)) => y
656
657(MOV(W|WZ)reg y:(MOV(WZ|W)reg x)) => (MOV(W|WZ)reg x)
658
659// Truncate then logical then truncate: omit first, lesser or equal truncate
660(MOVWZreg ((OR|XOR|AND) <t> x (MOVWZreg y))) => (MOVWZreg ((OR|XOR|AND) <t> x y))
661(MOVHZreg ((OR|XOR|AND) <t> x (MOVWZreg y))) => (MOVHZreg ((OR|XOR|AND) <t> x y))
662(MOVHZreg ((OR|XOR|AND) <t> x (MOVHZreg y))) => (MOVHZreg ((OR|XOR|AND) <t> x y))
663(MOVBZreg ((OR|XOR|AND) <t> x (MOVWZreg y))) => (MOVBZreg ((OR|XOR|AND) <t> x y))
664(MOVBZreg ((OR|XOR|AND) <t> x (MOVHZreg y))) => (MOVBZreg ((OR|XOR|AND) <t> x y))
665(MOVBZreg ((OR|XOR|AND) <t> x (MOVBZreg y))) => (MOVBZreg ((OR|XOR|AND) <t> x y))
666
667(MOV(B|H|W)Zreg z:(Select0 (ANDCCconst [c] (MOVBZload ptr x)))) => z
668(MOV(B|H|W)Zreg z:(AND y (MOV(B|H|W)Zload ptr x))) => z
669(MOV(H|W)Zreg z:(Select0 (ANDCCconst [c] (MOVHZload ptr x)))) => z
670(MOVWZreg z:(Select0 (ANDCCconst [c] (MOVWZload ptr x)))) => z
671
672// Arithmetic constant ops
673
674(ADD x (MOVDconst <t> [c])) && is32Bit(c) && !t.IsPtr() => (ADDconst [c] x)
675(ADDconst [c] (ADDconst [d] x)) && is32Bit(c+d) => (ADDconst [c+d] x)
676(ADDconst [0] x) => x
677(SUB x (MOVDconst [c])) && is32Bit(-c) => (ADDconst [-c] x)
678
679(ADDconst [c] (MOVDaddr [d] {sym} x)) && is32Bit(c+int64(d)) => (MOVDaddr [int32(c+int64(d))] {sym} x)
680(ADDconst [c] x:(SP)) && is32Bit(c) => (MOVDaddr [int32(c)] x) // so it is rematerializeable
681
682(MULL(W|D) x (MOVDconst [c])) && is16Bit(c) => (MULL(W|D)const [int32(c)] x)
683
684// Subtract from (with carry, but ignored) constant.
685// Note, these clobber the carry bit.
686(SUB (MOVDconst [c]) x) && is32Bit(c) => (SUBFCconst [c] x)
687(SUBFCconst [c] (NEG x)) => (ADDconst [c] x)
688(SUBFCconst [c] (SUBFCconst [d] x)) && is32Bit(c-d) => (ADDconst [c-d] x)
689(SUBFCconst [0] x) => (NEG x)
690(ADDconst [c] (SUBFCconst [d] x)) && is32Bit(c+d) => (SUBFCconst [c+d] x)
691(NEG (ADDconst [c] x)) && is32Bit(-c) => (SUBFCconst [-c] x)
692(NEG (SUBFCconst [c] x)) && is32Bit(-c) => (ADDconst [-c] x)
693(NEG (SUB x y)) => (SUB y x)
694(NEG (NEG x)) => x
695
696// Use register moves instead of stores and loads to move int<=>float values
697// Common with math Float64bits, Float64frombits
698(MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr x _)) => (MFVSRD x)
699(FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr x _)) => (MTVSRD x)
700
701(FMOVDstore [off] {sym} ptr (MTVSRD x) mem) => (MOVDstore [off] {sym} ptr x mem)
702(MOVDstore [off] {sym} ptr (MFVSRD x) mem) => (FMOVDstore [off] {sym} ptr x mem)
703
704(MTVSRD (MOVDconst [c])) && !math.IsNaN(math.Float64frombits(uint64(c))) => (FMOVDconst [math.Float64frombits(uint64(c))])
705(MFVSRD (FMOVDconst [c])) => (MOVDconst [int64(math.Float64bits(c))])
706
707(MTVSRD x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (FMOVDload [off] {sym} ptr mem)
708(MFVSRD x:(FMOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVDload [off] {sym} ptr mem)
709
710// Rules for MOV* or FMOV* ops determine when indexed (MOV*loadidx or MOV*storeidx)
711// or non-indexed (MOV*load or MOV*store) should be used. Indexed instructions
712// require an extra instruction and register to load the index so non-indexed is preferred.
713// Indexed ops generate indexed load or store instructions for all GOPPC64 values.
714// Non-indexed ops generate DS-form loads and stores when the offset fits in 16 bits,
715// and on power8 and power9, a multiple of 4 is required for MOVW and MOVD ops.
716// On power10, prefixed loads and stores can be used for offsets > 16 bits and <= 32 bits.
717// and support for PC relative addressing must be available if relocation is needed.
718// On power10, the assembler will determine when to use DS-form or prefixed
719// instructions for non-indexed ops depending on the value of the offset.
720//
721// Fold offsets for stores.
722(MOV(D|W|H|B)store [off1] {sym} (ADDconst [off2] x) val mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (MOV(D|W|H|B)store [off1+int32(off2)] {sym} x val mem)
723
724(FMOV(S|D)store [off1] {sym} (ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (FMOV(S|D)store [off1+int32(off2)] {sym} ptr val mem)
725
726// Fold address into load/store.
727// If power10 with PCRel is not available, then
728// the assembler needs to generate several instructions and use
729// temp register for accessing global, and each time it will reload
730// the temp register. So don't fold address of global in that case if there is more than
731// one use.
732(MOV(B|H|W|D)store [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
733 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
734 (MOV(B|H|W|D)store [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
735
736(FMOV(S|D)store [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
737 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
738 (FMOV(S|D)store [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
739
740(MOV(B|H|W)Zload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
741 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
742 (MOV(B|H|W)Zload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
743(MOV(H|W|D)load [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
744 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
745 (MOV(H|W|D)load [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
746(FMOV(S|D)load [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
747 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
748 (FMOV(S|D)load [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
749
750// Fold offsets for loads.
751(FMOV(S|D)load [off1] {sym} (ADDconst [off2] ptr) mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (FMOV(S|D)load [off1+int32(off2)] {sym} ptr mem)
752
753(MOV(D|W|WZ|H|HZ|BZ)load [off1] {sym} (ADDconst [off2] x) mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (MOV(D|W|WZ|H|HZ|BZ)load [off1+int32(off2)] {sym} x mem)
754
755// Determine load + addressing that can be done as a register indexed load
756(MOV(D|W|WZ|H|HZ|BZ)load [0] {sym} p:(ADD ptr idx) mem) && sym == nil && p.Uses == 1 => (MOV(D|W|WZ|H|HZ|BZ)loadidx ptr idx mem)
757
758// See comments above concerning selection of indexed vs. non-indexed ops.
759// These cases don't have relocation.
760(MOV(D|W)loadidx ptr (MOVDconst [c]) mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(D|W)load [int32(c)] ptr mem)
761(MOV(WZ|H|HZ|BZ)loadidx ptr (MOVDconst [c]) mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(WZ|H|HZ|BZ)load [int32(c)] ptr mem)
762(MOV(D|W)loadidx (MOVDconst [c]) ptr mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(D|W)load [int32(c)] ptr mem)
763(MOV(WZ|H|HZ|BZ)loadidx (MOVDconst [c]) ptr mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(WZ|H|HZ|BZ)load [int32(c)] ptr mem)
764
765// Store of zero => storezero
766(MOV(D|W|H|B)store [off] {sym} ptr (MOVDconst [0]) mem) => (MOV(D|W|H|B)storezero [off] {sym} ptr mem)
767
768// Fold offsets for storezero
769(MOV(D|W|H|B)storezero [off1] {sym} (ADDconst [off2] x) mem) && ((supportsPPC64PCRel() && is32Bit(int64(off1)+off2)) || (is16Bit(int64(off1)+off2))) =>
770 (MOV(D|W|H|B)storezero [off1+int32(off2)] {sym} x mem)
771
772// Stores with addressing that can be done as indexed stores
773(MOV(D|W|H|B)store [0] {sym} p:(ADD ptr idx) val mem) && sym == nil && p.Uses == 1 => (MOV(D|W|H|B)storeidx ptr idx val mem)
774
775(MOVDstoreidx ptr (MOVDconst [c]) val mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOVDstore [int32(c)] ptr val mem)
776(MOV(W|H|B)storeidx ptr (MOVDconst [c]) val mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(W|H|B)store [int32(c)] ptr val mem)
777(MOVDstoreidx (MOVDconst [c]) ptr val mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOVDstore [int32(c)] ptr val mem)
778(MOV(W|H|B)storeidx (MOVDconst [c]) ptr val mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(W|H|B)store [int32(c)] ptr val mem)
779
780// Fold symbols into storezero
781(MOV(D|W|H|B)storezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2)
782 && ((is16Bit(int64(off1+off2)) && (x.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
783 (MOV(D|W|H|B)storezero [off1+off2] {mergeSym(sym1,sym2)} x mem)
784
785// atomic intrinsics
786(AtomicLoad(8|32|64|Ptr) ptr mem) => (LoweredAtomicLoad(8|32|64|Ptr) [1] ptr mem)
787(AtomicLoadAcq(32|64) ptr mem) => (LoweredAtomicLoad(32|64) [0] ptr mem)
788
789(AtomicStore(8|32|64) ptr val mem) => (LoweredAtomicStore(8|32|64) [1] ptr val mem)
790(AtomicStoreRel(32|64) ptr val mem) => (LoweredAtomicStore(32|64) [0] ptr val mem)
791
792(AtomicExchange(32|64) ...) => (LoweredAtomicExchange(32|64) ...)
793
794(AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...)
795
796(AtomicCompareAndSwap(32|64) ptr old new_ mem) => (LoweredAtomicCas(32|64) [1] ptr old new_ mem)
797(AtomicCompareAndSwapRel32 ptr old new_ mem) => (LoweredAtomicCas32 [0] ptr old new_ mem)
798
799(AtomicAnd(8|32) ...) => (LoweredAtomicAnd(8|32) ...)
800(AtomicOr(8|32) ...) => (LoweredAtomicOr(8|32) ...)
801
802(Slicemask <t> x) => (SRADconst (NEG <t> x) [63])
803(Select0 (ANDCCconst [1] z:(SRADconst [63] x))) && z.Uses == 1 => (SRDconst [63] x)
804
805// Note that MOV??reg returns a 64-bit int, x is not necessarily that wide
806// This may interact with other patterns in the future. (Compare with arm64)
807(MOV(B|H|W)Zreg x:(MOVBZload _ _)) => x
808(MOV(B|H|W)Zreg x:(MOVBZloadidx _ _ _)) => x
809(MOV(H|W)Zreg x:(MOVHZload _ _)) => x
810(MOV(H|W)Zreg x:(MOVHZloadidx _ _ _)) => x
811(MOV(H|W)reg x:(MOVHload _ _)) => x
812(MOV(H|W)reg x:(MOVHloadidx _ _ _)) => x
813(MOV(WZ|W)reg x:(MOV(WZ|W)load _ _)) => x
814(MOV(WZ|W)reg x:(MOV(WZ|W)loadidx _ _ _)) => x
815(MOV(B|W)Zreg x:(Select0 (LoweredAtomicLoad(8|32) _ _))) => x
816
817// don't extend if argument is already extended
818(MOVBreg x:(Arg <t>)) && is8BitInt(t) && t.IsSigned() => x
819(MOVBZreg x:(Arg <t>)) && is8BitInt(t) && !t.IsSigned() => x
820(MOVHreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && t.IsSigned() => x
821(MOVHZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && !t.IsSigned() => x
822(MOVWreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && t.IsSigned() => x
823(MOVWZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !t.IsSigned() => x
824
825(MOVBZreg (MOVDconst [c])) => (MOVDconst [int64(uint8(c))])
826(MOVBreg (MOVDconst [c])) => (MOVDconst [int64(int8(c))])
827(MOVHZreg (MOVDconst [c])) => (MOVDconst [int64(uint16(c))])
828(MOVHreg (MOVDconst [c])) => (MOVDconst [int64(int16(c))])
829(MOVWreg (MOVDconst [c])) => (MOVDconst [int64(int32(c))])
830(MOVWZreg (MOVDconst [c])) => (MOVDconst [int64(uint32(c))])
831
832// Implement clrsldi and clrslwi extended mnemonics as described in
833// ISA 3.0 section C.8. AuxInt field contains values needed for
834// the instructions, packed together since there is only one available.
835(SLDconst [c] z:(MOVBZreg x)) && c < 8 && z.Uses == 1 => (CLRLSLDI [newPPC64ShiftAuxInt(c,56,63,64)] x)
836(SLDconst [c] z:(MOVHZreg x)) && c < 16 && z.Uses == 1 => (CLRLSLDI [newPPC64ShiftAuxInt(c,48,63,64)] x)
837(SLDconst [c] z:(MOVWZreg x)) && c < 32 && z.Uses == 1 => (CLRLSLDI [newPPC64ShiftAuxInt(c,32,63,64)] x)
838
839(SLDconst [c] z:(Select0 (ANDCCconst [d] x))) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c <= (64-getPPC64ShiftMaskLength(d)) => (CLRLSLDI [newPPC64ShiftAuxInt(c,64-getPPC64ShiftMaskLength(d),63,64)] x)
840(SLDconst [c] z:(AND (MOVDconst [d]) x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(64-getPPC64ShiftMaskLength(d)) => (CLRLSLDI [newPPC64ShiftAuxInt(c,64-getPPC64ShiftMaskLength(d),63,64)] x)
841(SLWconst [c] z:(MOVBZreg x)) && z.Uses == 1 && c < 8 => (CLRLSLWI [newPPC64ShiftAuxInt(c,24,31,32)] x)
842(SLWconst [c] z:(MOVHZreg x)) && z.Uses == 1 && c < 16 => (CLRLSLWI [newPPC64ShiftAuxInt(c,16,31,32)] x)
843(SLWconst [c] z:(Select0 (ANDCCconst [d] x))) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(32-getPPC64ShiftMaskLength(d)) => (CLRLSLWI [newPPC64ShiftAuxInt(c,32-getPPC64ShiftMaskLength(d),31,32)] x)
844(SLWconst [c] z:(AND (MOVDconst [d]) x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(32-getPPC64ShiftMaskLength(d)) => (CLRLSLWI [newPPC64ShiftAuxInt(c,32-getPPC64ShiftMaskLength(d),31,32)] x)
845// special case for power9
846(SL(W|D)const [c] z:(MOVWreg x)) && c < 32 && buildcfg.GOPPC64 >= 9 => (EXTSWSLconst [c] x)
847
848// Lose widening ops fed to stores
849(MOVBstore [off] {sym} ptr (MOV(B|BZ|H|HZ|W|WZ)reg x) mem) => (MOVBstore [off] {sym} ptr x mem)
850(MOVHstore [off] {sym} ptr (MOV(H|HZ|W|WZ)reg x) mem) => (MOVHstore [off] {sym} ptr x mem)
851(MOVWstore [off] {sym} ptr (MOV(W|WZ)reg x) mem) => (MOVWstore [off] {sym} ptr x mem)
852(MOVBstore [off] {sym} ptr (SRWconst (MOV(H|HZ)reg x) [c]) mem) && c <= 8 => (MOVBstore [off] {sym} ptr (SRWconst <typ.UInt32> x [c]) mem)
853(MOVBstore [off] {sym} ptr (SRWconst (MOV(W|WZ)reg x) [c]) mem) && c <= 24 => (MOVBstore [off] {sym} ptr (SRWconst <typ.UInt32> x [c]) mem)
854(MOVBstoreidx ptr idx (MOV(B|BZ|H|HZ|W|WZ)reg x) mem) => (MOVBstoreidx ptr idx x mem)
855(MOVHstoreidx ptr idx (MOV(H|HZ|W|WZ)reg x) mem) => (MOVHstoreidx ptr idx x mem)
856(MOVWstoreidx ptr idx (MOV(W|WZ)reg x) mem) => (MOVWstoreidx ptr idx x mem)
857(MOVBstoreidx ptr idx (SRWconst (MOV(H|HZ)reg x) [c]) mem) && c <= 8 => (MOVBstoreidx ptr idx (SRWconst <typ.UInt32> x [c]) mem)
858(MOVBstoreidx ptr idx (SRWconst (MOV(W|WZ)reg x) [c]) mem) && c <= 24 => (MOVBstoreidx ptr idx (SRWconst <typ.UInt32> x [c]) mem)
859(MOVHBRstore ptr (MOV(H|HZ|W|WZ)reg x) mem) => (MOVHBRstore ptr x mem)
860(MOVWBRstore ptr (MOV(W|WZ)reg x) mem) => (MOVWBRstore ptr x mem)
861
862// Lose W-widening ops fed to compare-W
863(CMP(W|WU) x (MOV(W|WZ)reg y)) => (CMP(W|WU) x y)
864(CMP(W|WU) (MOV(W|WZ)reg x) y) => (CMP(W|WU) x y)
865
866(CMP x (MOVDconst [c])) && is16Bit(c) => (CMPconst x [c])
867(CMP (MOVDconst [c]) y) && is16Bit(c) => (InvertFlags (CMPconst y [c]))
868(CMPW x (MOVDconst [c])) && is16Bit(c) => (CMPWconst x [int32(c)])
869(CMPW (MOVDconst [c]) y) && is16Bit(c) => (InvertFlags (CMPWconst y [int32(c)]))
870
871(CMPU x (MOVDconst [c])) && isU16Bit(c) => (CMPUconst x [c])
872(CMPU (MOVDconst [c]) y) && isU16Bit(c) => (InvertFlags (CMPUconst y [c]))
873(CMPWU x (MOVDconst [c])) && isU16Bit(c) => (CMPWUconst x [int32(c)])
874(CMPWU (MOVDconst [c]) y) && isU16Bit(c) => (InvertFlags (CMPWUconst y [int32(c)]))
875
876// Canonicalize the order of arguments to comparisons - helps with CSE.
877((CMP|CMPW|CMPU|CMPWU) x y) && canonLessThan(x,y) => (InvertFlags ((CMP|CMPW|CMPU|CMPWU) y x))
878
879// SETBC auxInt values 0=LT 1=GT 2=EQ Crbit==1 ? 1 : 0
880// SETBCR auxInt values 0=LT 1=GT 2=EQ Crbit==1 ? 0 : 1
881(Equal cmp) => (SETBC [2] cmp)
882(NotEqual cmp) => (SETBCR [2] cmp)
883(LessThan cmp) => (SETBC [0] cmp)
884(FLessThan cmp) => (SETBC [0] cmp)
885(FLessEqual cmp) => (OR (SETBC [2] cmp) (SETBC [0] cmp))
886(GreaterEqual cmp) => (SETBCR [0] cmp)
887(GreaterThan cmp) => (SETBC [1] cmp)
888(FGreaterEqual cmp) => (OR (SETBC [2] cmp) (SETBC [1] cmp))
889(FGreaterThan cmp) => (SETBC [1] cmp)
890(LessEqual cmp) => (SETBCR [1] cmp)
891
892(SETBC [0] (FlagLT)) => (MOVDconst [1])
893(SETBC [0] (Flag(GT|EQ))) => (MOVDconst [0])
894(SETBC [1] (FlagGT)) => (MOVDconst [1])
895(SETBC [1] (Flag(LT|EQ))) => (MOVDconst [0])
896(SETBC [2] (FlagEQ)) => (MOVDconst [1])
897(SETBC [2] (Flag(LT|GT))) => (MOVDconst [0])
898
899(SETBCR [0] (FlagLT)) => (MOVDconst [0])
900(SETBCR [0] (Flag(GT|EQ))) => (MOVDconst [1])
901(SETBCR [1] (FlagGT)) => (MOVDconst [0])
902(SETBCR [1] (Flag(LT|EQ))) => (MOVDconst [1])
903(SETBCR [2] (FlagEQ)) => (MOVDconst [0])
904(SETBCR [2] (Flag(LT|GT))) => (MOVDconst [1])
905
906(SETBC [0] (InvertFlags bool)) => (SETBC [1] bool)
907(SETBC [1] (InvertFlags bool)) => (SETBC [0] bool)
908(SETBC [2] (InvertFlags bool)) => (SETBC [2] bool)
909
910(SETBCR [0] (InvertFlags bool)) => (SETBCR [1] bool)
911(SETBCR [1] (InvertFlags bool)) => (SETBCR [0] bool)
912(SETBCR [2] (InvertFlags bool)) => (SETBCR [2] bool)
913
914// ISEL auxInt values 0=LT 1=GT 2=EQ arg2 ? arg0 : arg1
915// ISEL auxInt values 4=GE 5=LE 6=NE !arg2 ? arg1 : arg0
916
917(ISEL [2] x _ (FlagEQ)) => x
918(ISEL [2] _ y (Flag(LT|GT))) => y
919
920(ISEL [6] _ y (FlagEQ)) => y
921(ISEL [6] x _ (Flag(LT|GT))) => x
922
923(ISEL [0] _ y (Flag(EQ|GT))) => y
924(ISEL [0] x _ (FlagLT)) => x
925
926(ISEL [5] _ x (Flag(EQ|LT))) => x
927(ISEL [5] y _ (FlagGT)) => y
928
929(ISEL [1] _ y (Flag(EQ|LT))) => y
930(ISEL [1] x _ (FlagGT)) => x
931
932(ISEL [4] x _ (Flag(EQ|GT))) => x
933(ISEL [4] _ y (FlagLT)) => y
934
935(ISEL [2] x y ((CMP|CMPW)const [0] (Select0 (ANDCCconst [n] z)))) => (ISEL [2] x y (Select1 <types.TypeFlags> (ANDCCconst [n] z )))
936(ISEL [6] x y ((CMP|CMPW)const [0] (Select0 (ANDCCconst [n] z)))) => (ISEL [6] x y (Select1 <types.TypeFlags> (ANDCCconst [n] z )))
937(SETBC [n] (InvertFlags bool)) => (SETBCR [n] bool)
938(SETBCR [n] (InvertFlags bool)) => (SETBC [n] bool)
939
940(ISEL [n] x y (InvertFlags bool)) && n%4 == 0 => (ISEL [n+1] x y bool)
941(ISEL [n] x y (InvertFlags bool)) && n%4 == 1 => (ISEL [n-1] x y bool)
942(ISEL [n] x y (InvertFlags bool)) && n%4 == 2 => (ISEL [n] x y bool)
943(XORconst [1] (SETBCR [n] cmp)) => (SETBC [n] cmp)
944(XORconst [1] (SETBC [n] cmp)) => (SETBCR [n] cmp)
945
946(SETBC [2] ((CMP|CMPW)const [0] (Select0 (ANDCCconst [1] z)))) => (XORconst [1] (Select0 <typ.UInt64> (ANDCCconst [1] z )))
947(SETBCR [2] ((CMP|CMPW)const [0] (Select0 (ANDCCconst [1] z)))) => (Select0 <typ.UInt64> (ANDCCconst [1] z ))
948
949(SETBC [2] (CMPWconst [0] (Select0 (ANDCCconst [n] z)))) => (SETBC [2] (Select1 <types.TypeFlags> (ANDCCconst [n] z )))
950(SETBCR [2] (CMPWconst [0] (Select0 (ANDCCconst [n] z)))) => (SETBCR [2] (Select1 <types.TypeFlags> (ANDCCconst [n] z )))
951
952// Only CMPconst for these in case AND|OR|XOR result is > 32 bits
953(SETBC [2] (CMPconst [0] a:(AND y z))) && a.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (ANDCC y z )))
954(SETBCR [2] (CMPconst [0] a:(AND y z))) && a.Uses == 1 => (SETBCR [2] (Select1 <types.TypeFlags> (ANDCC y z )))
955
956(SETBC [2] (CMPconst [0] o:(OR y z))) && o.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (ORCC y z )))
957(SETBCR [2] (CMPconst [0] o:(OR y z))) && o.Uses == 1 => (SETBCR [2] (Select1 <types.TypeFlags> (ORCC y z )))
958
959(SETBC [2] (CMPconst [0] a:(XOR y z))) && a.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (XORCC y z )))
960(SETBCR [2] (CMPconst [0] a:(XOR y z))) && a.Uses == 1 => (SETBCR [2] (Select1 <types.TypeFlags> (XORCC y z )))
961
962// A particular pattern seen in cgo code:
963(AND (MOVDconst [c]) x:(MOVBZload _ _)) => (Select0 (ANDCCconst [c&0xFF] x))
964
965// floating point negative abs
966(FNEG (F(ABS|NABS) x)) => (F(NABS|ABS) x)
967
968// floating-point fused multiply-add/sub
969(F(ADD|SUB) (FMUL x y) z) && x.Block.Func.useFMA(v) => (FM(ADD|SUB) x y z)
970(F(ADDS|SUBS) (FMULS x y) z) && x.Block.Func.useFMA(v) => (FM(ADDS|SUBS) x y z)
971
972// Arch-specific inlining for small or disjoint runtime.memmove
973(SelectN [0] call:(CALLstatic {sym} s1:(MOVDstore _ (MOVDconst [sz]) s2:(MOVDstore _ src s3:(MOVDstore {t} _ dst mem)))))
974 && sz >= 0
975 && isSameCall(sym, "runtime.memmove")
976 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1
977 && isInlinableMemmove(dst, src, sz, config)
978 && clobber(s1, s2, s3, call)
979 => (Move [sz] dst src mem)
980
981// Match post-lowering calls, register version.
982(SelectN [0] call:(CALLstatic {sym} dst src (MOVDconst [sz]) mem))
983 && sz >= 0
984 && isSameCall(sym, "runtime.memmove")
985 && call.Uses == 1
986 && isInlinableMemmove(dst, src, sz, config)
987 && clobber(call)
988 => (Move [sz] dst src mem)
989
990// Prefetch instructions (TH specified using aux field)
991// For DCBT Ra,Rb,TH, A value of TH indicates:
992// 0, hint this cache line will be used soon. (PrefetchCache)
993// 16, hint this cache line will not be used for long. (PrefetchCacheStreamed)
994// See ISA 3.0 Book II 4.3.2 for more detail. https://openpower.foundation/specifications/isa/
995(PrefetchCache ptr mem) => (DCBT ptr mem [0])
996(PrefetchCacheStreamed ptr mem) => (DCBT ptr mem [16])
997
998// Use byte reverse instructions on Power10
999(Bswap(16|32|64) x) && buildcfg.GOPPC64>=10 => (BR(H|W|D) x)
1000
1001// Fold bit reversal into loads.
1002(BR(W|H) x:(MOV(W|H)Zload [off] {sym} ptr mem)) && x.Uses == 1 => @x.Block (MOV(W|H)BRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1003(BR(W|H) x:(MOV(W|H)Zloadidx ptr idx mem)) && x.Uses == 1 => @x.Block (MOV(W|H)BRloadidx ptr idx mem)
1004(BRD x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 => @x.Block (MOVDBRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1005(BRD x:(MOVDloadidx ptr idx mem)) && x.Uses == 1 => @x.Block (MOVDBRloadidx ptr idx mem)
1006
1007// Fold bit reversal into stores.
1008(MOV(D|W|H)store [off] {sym} ptr r:(BR(D|W|H) val) mem) && r.Uses == 1 => (MOV(D|W|H)BRstore (MOVDaddr <ptr.Type> [off] {sym} ptr) val mem)
1009(MOV(D|W|H)storeidx ptr idx r:(BR(D|W|H) val) mem) && r.Uses == 1 => (MOV(D|W|H)BRstoreidx ptr idx val mem)
1010
1011// GOPPC64<10 rules.
1012// These Bswap operations should only be introduced by the memcombine pass in places where they can be folded into loads or stores.
1013(Bswap(32|16) x:(MOV(W|H)Zload [off] {sym} ptr mem)) => @x.Block (MOV(W|H)BRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1014(Bswap(32|16) x:(MOV(W|H)Zloadidx ptr idx mem)) => @x.Block (MOV(W|H)BRloadidx ptr idx mem)
1015(Bswap64 x:(MOVDload [off] {sym} ptr mem)) => @x.Block (MOVDBRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1016(Bswap64 x:(MOVDloadidx ptr idx mem)) => @x.Block (MOVDBRloadidx ptr idx mem)
1017(MOV(D|W|H)store [off] {sym} ptr (Bswap(64|32|16) val) mem) => (MOV(D|W|H)BRstore (MOVDaddr <ptr.Type> [off] {sym} ptr) val mem)
1018(MOV(D|W|H)storeidx ptr idx (Bswap(64|32|16) val) mem) => (MOV(D|W|H)BRstoreidx ptr idx val mem)
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