1// Copyright 2022 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5// This file contains rules used by the laterLower pass.
6// These are often the exact inverse of rules in ARM64.rules.
7
8(ADDconst [c] x) && !isARM64addcon(c) => (ADD x (MOVDconst [c]))
9(SUBconst [c] x) && !isARM64addcon(c) => (SUB x (MOVDconst [c]))
10(ANDconst [c] x) && !isARM64bitcon(uint64(c)) => (AND x (MOVDconst [c]))
11(ORconst [c] x) && !isARM64bitcon(uint64(c)) => (OR x (MOVDconst [c]))
12(XORconst [c] x) && !isARM64bitcon(uint64(c)) => (XOR x (MOVDconst [c]))
13(TSTconst [c] x) && !isARM64bitcon(uint64(c)) => (TST x (MOVDconst [c]))
14(TSTWconst [c] x) && !isARM64bitcon(uint64(c)|uint64(c)<<32) => (TSTW x (MOVDconst [int64(c)]))
15
16(CMPconst [c] x) && !isARM64addcon(c) => (CMP x (MOVDconst [c]))
17(CMPWconst [c] x) && !isARM64addcon(int64(c)) => (CMPW x (MOVDconst [int64(c)]))
18(CMNconst [c] x) && !isARM64addcon(c) => (CMN x (MOVDconst [c]))
19(CMNWconst [c] x) && !isARM64addcon(int64(c)) => (CMNW x (MOVDconst [int64(c)]))
20
21(ADDSconstflags [c] x) && !isARM64addcon(c) => (ADDSflags x (MOVDconst [c]))
22
23// These rules remove unneeded sign/zero extensions.
24// They occur in late lower because they rely on the fact
25// that their arguments don't get rewritten to a non-extended opcode instead.
26
27// Boolean-generating instructions (NOTE: NOT all boolean Values) always
28// zero upper bit of the register; no need to zero-extend
29(MOVBUreg x:((Equal|NotEqual|LessThan|LessThanU|LessThanF|LessEqual|LessEqualU|LessEqualF|GreaterThan|GreaterThanU|GreaterThanF|GreaterEqual|GreaterEqualU|GreaterEqualF) _)) => x
30
31// omit unsigned extension
32(MOVWUreg x) && zeroUpper32Bits(x, 3) => x
33
34// don't extend after proper load
35(MOVBreg x:(MOVBload _ _)) => (MOVDreg x)
36(MOVBUreg x:(MOVBUload _ _)) => (MOVDreg x)
37(MOVHreg x:(MOVBload _ _)) => (MOVDreg x)
38(MOVHreg x:(MOVBUload _ _)) => (MOVDreg x)
39(MOVHreg x:(MOVHload _ _)) => (MOVDreg x)
40(MOVHUreg x:(MOVBUload _ _)) => (MOVDreg x)
41(MOVHUreg x:(MOVHUload _ _)) => (MOVDreg x)
42(MOVWreg x:(MOVBload _ _)) => (MOVDreg x)
43(MOVWreg x:(MOVBUload _ _)) => (MOVDreg x)
44(MOVWreg x:(MOVHload _ _)) => (MOVDreg x)
45(MOVWreg x:(MOVHUload _ _)) => (MOVDreg x)
46(MOVWreg x:(MOVWload _ _)) => (MOVDreg x)
47(MOVWUreg x:(MOVBUload _ _)) => (MOVDreg x)
48(MOVWUreg x:(MOVHUload _ _)) => (MOVDreg x)
49(MOVWUreg x:(MOVWUload _ _)) => (MOVDreg x)
50(MOVBreg x:(MOVBloadidx _ _ _)) => (MOVDreg x)
51(MOVBUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x)
52(MOVHreg x:(MOVBloadidx _ _ _)) => (MOVDreg x)
53(MOVHreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x)
54(MOVHreg x:(MOVHloadidx _ _ _)) => (MOVDreg x)
55(MOVHUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x)
56(MOVHUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x)
57(MOVWreg x:(MOVBloadidx _ _ _)) => (MOVDreg x)
58(MOVWreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x)
59(MOVWreg x:(MOVHloadidx _ _ _)) => (MOVDreg x)
60(MOVWreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x)
61(MOVWreg x:(MOVWloadidx _ _ _)) => (MOVDreg x)
62(MOVWUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x)
63(MOVWUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x)
64(MOVWUreg x:(MOVWUloadidx _ _ _)) => (MOVDreg x)
65(MOVHreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x)
66(MOVHUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x)
67(MOVWreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x)
68(MOVWreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x)
69(MOVWreg x:(MOVWloadidx4 _ _ _)) => (MOVDreg x)
70(MOVWUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x)
71(MOVWUreg x:(MOVWUloadidx4 _ _ _)) => (MOVDreg x)
72
73// fold double extensions
74(MOVBreg x:(MOVBreg _)) => (MOVDreg x)
75(MOVBUreg x:(MOVBUreg _)) => (MOVDreg x)
76(MOVHreg x:(MOVBreg _)) => (MOVDreg x)
77(MOVHreg x:(MOVBUreg _)) => (MOVDreg x)
78(MOVHreg x:(MOVHreg _)) => (MOVDreg x)
79(MOVHUreg x:(MOVBUreg _)) => (MOVDreg x)
80(MOVHUreg x:(MOVHUreg _)) => (MOVDreg x)
81(MOVWreg x:(MOVBreg _)) => (MOVDreg x)
82(MOVWreg x:(MOVBUreg _)) => (MOVDreg x)
83(MOVWreg x:(MOVHreg _)) => (MOVDreg x)
84(MOVWreg x:(MOVWreg _)) => (MOVDreg x)
85(MOVWUreg x:(MOVBUreg _)) => (MOVDreg x)
86(MOVWUreg x:(MOVHUreg _)) => (MOVDreg x)
87(MOVWUreg x:(MOVWUreg _)) => (MOVDreg x)
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